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august 200 4 asm4sstvf16859 rev 2.0 alliance semiconductor 2 575, augustine drive ? santa clara, ca ? tel: 408.855.4900 ? fax: 408.855.4999 ? www.alsc.com notice: the information in this document is subject to change without notice. ddr 13 - bit to 26 - bit registered buffer features ? differential clock signals. ? meets sstl_2 class ii specifications on outputs. ? l ow voltage operation: v dd = 2.3v to 2.7v. ? available in 64 - pin tssop, 64 - pin tvsop, and 56 - pin vfqfn packages. product descriptio n the asm4sstvf16859 is a universal 13/26 bit register (d f/f based), designed for 2.3v to 2.7v v dd operation. the device supports sstl_2 i/o levels, and is fully compliant with the jedec jc40, jc42.5 ddr i specifications covering pc1600, pc 2100, pc27 00, and pc3200 operational ranges ( ddr 400 C applications ? ? ? ? ? ?
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 1 of 16 block diagram clk clkb resetb d1 vref r clk d1 q1a q1b to 12 other channels asm4sstvf16859
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 2 of 16 pin configurations 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 q13a q12a q1 1 a q10a q9a vddq gnd q8a q7a q6a q5a q4a q3a q2a gnd q1a q13b vddq q12b q1 1 b q10b q9b q8b q7b q6b gnd vddq q5b q4b q3b q2b q1b vddq gnd d13 d12 vdd vddq gnd d1 1 d10 d9 gnd d8 d7 resetb gnd clkb clk vddq vdd vref d6 gnd d5 d4 d3 gnd vddq vdd d2 d1 gnd vddq a s m 4 s s t v f 1 6 8 5 9 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 42 41 40 39 38 37 36 35 34 33 32 31 30 29 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 asm4sstvf16859 64-pin tssop 6.10 mm body , 0.50 mm pitch 56-pin vfqfn (mlf2)
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 3 of 16 pin descriptions 64 - pin tssop pin # pin name type description 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 1 4, 16, 17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 32 q (13:1) o data output. 7, 15, 26, 34, 39, 43, 50, 54, 58, 63 gnd p ground to entire chip. 6, 18, 27, 33, 38, 47, 59, 64 vddq p output supply voltage, 2.5v nominal. 35, 36, 40, 41, 42, 44, 52, 53 , 55, 56, 57, 61, 62 d(13:1) i data input. 48 clk i positive master clock input. 49 clkb i negative master clock input. 37, 46, 60 vdd p core supply voltage, 2.5v nominal. 51 resetb i rest active low. 45 vref i input reference voltage, 1.25v nominal. 56 - pin mlf2 pin # pin name type description 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 50, 51, 52, 53, 54, 56 q (13:1) o data output. 37, 48 gnd p ground to entire chip. 9, 17, 23, 27, 34, 44, 49, 55 vddq p output supply voltage, 2.5v nominal. 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47 d(13:1) i data input. 35 clk i positive master clock input. 36 clkb i negative master clock input. 26, 33, 45 vdd p core supply voltage, 2.5v nominal. 38 resetb i rest active l ow. 32 vref i input reference voltage, 1.25v nominal. - center pad p ground (vfqfn package only)
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 4 of 16 truth table inputs q outputs resetb clk clkb d q l x or floating x or floating x or floating l h h h h l l h l or h l or h x q 0 2 note: 1. h=hig 1 absolute maximum ratings parameter min max unit storage temperature - 65 +150 c supply voltage - 0.5 3.6 v input voltage 1 - 0.5 v dd + 0.5 v output voltage 1,2 - 0.5 v dd + 0.5 v input clamp current 50 ma output clamp current 50 ma continuous output current 50 ma vdd, vddq or gnd current/pin 100 ma package thermal impedance 3 55 c/w note: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this current will flow only when the output is in the high state level v 0 > v ddq. 3. the p ackage thermal impedance is calculated in accordance with jesd 51. these are stress ratings only and functional operation is not implied. exposure to absolute maximum ratings for prolonged periods can affect device reliability.
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 5 of 16 r ecomended operatin g conditions - ddri / ddr333 (pc1600, pc2100, pc2700) * parameter description min typ max unit v dd supply voltage 2.3 2.5 2.7 v v ddq i/o supply voltage 2.3 2.5 2.7 v v ref reference voltage 1.15 1.25 1.35 v v tt termination voltage v ref - 0.04 v ref v ref + 0.004 v v i input voltage 0 vdd v v ih(dc) dc input high voltage v ref + 0.15 v v ih(ac) ac input high voltage v ref + 0.31 v v il(dc) dc input low voltage v ref - 0.15 v v il(ac) ac input low voltage data inputs v ref - 0.31 v v ih input high vol tage level 1.7 v v il input low voltage level resetb 0.7 v v icr common mode input range clk 0.97 1.53 v v id differential input voltage clkb 0.36 v v ix cross - point voltage of differential clock pair (v ddq /2) - 0.2 (v ddq /2) +0.2 v i oh high - level output current - 20 ma i ol low - level output current 20 ma t a operating free - air temperature 0 70 c r ecomended operating conditions - ddri - 400 (pc3200) * parameter description min typ max units v dd supply voltage 2.5 2.6 2.7 v v ddq i/o supply volt age 2.5 2.6 2.7 v v ref reference voltage 1.25 1.3 1.35 v v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v v i input voltage 0 v ddq v v ih(dc) dc input high voltage v ref + 0.15 v v ih(ac) ac input high voltage v ref + 0.31 v v il(d c) dc input low voltage v ref - 0.15 v v il(ac) ac input low voltage data inputs v ref - 0.31 v v ih input high voltage level 1.7 v v il input low voltage level resetb 0.7 v v icr common mode input range 0.97 1.53 v v id differential input voltage clk, clkb 0.36 v v ix cross - point voltage of differential clock pair (v ddq /2) - 0.2 (v ddq /2) + 0.2 v i oh high - level output current - 16 ma i ol low - level output current 16 ma t a operating free - air temperature 0 70 ? c
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 6 of 16 * guaranteed by design. not 100% production tested. dc electrical characteristics - ddri / ddr333 (pc1600, pc2100, pc2700) t a = 0c to 70c, v dd = 2.5 0.2v, and v ddq = 2.5 0.2v (unless otherwise stated) guaranteed by design. not 100% production tested. symbol parameters test conditio ns v dd min typ max units v ik i i = - 18 ma 2.3 v - 1.2 v v oh i oh = - 100 ? a 2.3 v to 2.7 v v dd - 0.2 v i oh = - 16 ma 2.3 v 1.95 v v ol i ol = 100 ? a 2.3 v to 2.7 v 0.2 v i ol = 16 ma 2.3 v 0.35 v i i all inputs v i = v dd or gnd 2.7 v 5 ? a i dd standby (static) resetb = gnd 2.7 v 0.01 ? a operating (stat ic) v i = v ih(ac) or v il(ac) , resetb = v dd 2.7 v 25 ma i ddd dynamic operating (clock only) resetb = v dd , v i = v ih(ac) or v il(ac) , clk and clkb switching 50% duty cycle 2.7 v 30 ? a/clock mhz dynamic operating (per each data input) resetb = v dd , v i = v ih(ac) or v il(ac) , clk and clkb = switching 50% duty cycle one data input switching at half clock frequency, 50% duty cycle i o = 0 2.7 v 10 ?? /clock mhz/data input r oh output high i oh = - 20 ma 2.3 v to 2.7 v 7 20 w r ol output low i ol = 20 ma 2.3 v to 2.7 v 7 20 w r o(d) |r oh - r ol | each sepa rate bit i o = 20 ma, t a = 25 ? c 2.5 v 4 w c i data inputs v i = v ref 310 mv, v icr = 1.25 v, v i(pp) = 360 mv 2.5 v 2.5 3.5 pf clk and clkb 2.5 v 2.5 3.5 pf resetb v i = v dd or gnd 2.5v 2.5 3.5 pf
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 7 of 16 dc electrical characteristics - ddri - 400 (pc3200) t a = 0c to 70c, v dd = 2.6 0.2v, and v ddq = 2.6 0.2v (unless otherwise stated) guaranteed by design. not 100% production tested. symbol parameters test conditions v dd min typ max units v ik i i = - 18 ma 2.5 v - 1.2 v v oh i oh = - 100 ? a 2.5 v to 2.7 v v dd - 0.2 v i oh = - 8 ma 2.5 v 1.95 v v ol i ol = 100 ? a 2.5 v to 2.7 v 0.2 v i ol = 8 ma 2.5 v 0.35 v i i all inputs v i = v dd or gnd 2.7 v 5 ? a i dd standby (static) resetb = gnd 2.7 v 0.01 ? a operating (static ) v i = v ih(ac) or v il(ac) , resetb = v dd 2.7 v 25 ma i ddd dynamic operating (clock only) resetb = v dd , v i = v ih(ac) or v il(ac) , clk and clkb switching 50% duty cycle 2.7 v 30 ? a/clock mhz dynamic operating (per each data input) resetb = v dd , v i = v ih(ac) or v il(ac) , clk and clkb = switching 50% duty cycle; one data input switching at half clock frequency, 50% duty cycle i o = 0 2.7 v 10 ?? /clock mhz/data input r oh output high i oh = - 16 ma 2.5 v to 2.7 v 7 20 w r ol output low i ol = 16 ma 2.5 v to 2. 7 v 7 20 w r o(d) |r oh - r ol | each sepa rate bit i o = 20 ma, t a = 25 ? c 2.6 v 4 w data inputs 2.6 v 2.5 3.5 pf clk and clkb v i = v ref 310 mv, v icr = 1.25 v, v i(pp) = 360 mv 2.6 v 2.5 3.5 pf c i resetb v i = v dd or gnd 2.6v 2.5 3.5 pf
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 8 of 16 timin g requirements ** guaranteed by design. not 100% production tested. v ddq = 2.5v0.2v v ddq = 2.6v0.1v symbol parameters min max min max units f clock clock frequency 200 270 mhz t w pulse duration, ck, cklb high or low 2.5 2.5 ns t act * differenti al inputs active time 22 22 ns t inact * differential inputs inactive time 22 22 ns setup time, fast slew rate 0.75 0.4 t s setup time, slow slew rate data before clk ? , clkb ? 0.9 0.6 ns hold time, fast slew rate 0.75 0.4 t h hold time, slow slew rate data after clk ? , clkb ? 0.9 0.6 ns note: 1. data inputs must be low for a minimum time of t act max, after which resetb is taken high. 2. data and clock inputs must be held at valid levels (not floating) for a minimum time of t inact max after which resetb is taken low. 3. for data signal input slew rate >=v/ns 4. for data signal input slew rate >=0.5 v/ns and < 1v/ns 5. clk,clkb signals input slew rates are >=1v/ns switching characteristics - ddri / ddr333 (pc1600, pc2100, pc2700) ** vdd = 2.5 v 0.2 v symbol fro m (input) to (output) min typ max units f max 200 C C pd clk, clkb (tssop) q 1.1 2.8 ns clk, clkb (vfqfn[mlf2]) q 1.1 2.8 ns t phl resetb q C C switching characteristics - ddri - 400 (pc3200) ** vdd = 2.6 v 0.1 v symbol from (inpu t) to (output) min typ max units f max 210 mhz t pd clk, clkb (vfqfn[mlf2]) simultaneous switching q 1.1 2.2 ns t pdss q 2.48 ns t phl resetb q 3.5 ns *this parameter is not necessarily production tested. **over recom mended operating free - air temperatur e range unless otherwise noted.
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 9 of 16 parameter measurement information (v dd = 2.5 v 0.2 v ) voltage and current waveforms in the following waveforms, note that all input pulses are supplied by generators having the follo wing characteristics: prr 10 mhz, z o = 50 ? , input slew rate = 1 v/ns 20% (unless otherwise specified). the outputs are measured one at a time with one transition per measurement. v tt = v ref = v ddq /2. v ih = v ref + 310 mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. v il = v ref - 310 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. t plh and t phl are the same as t pd . input active and inactive times pulse duration setup and hold times v tt r l = 50 ? test point c l = 30 pf 1 load circuit from output under test 1 c l includes probe and jig capacitance. lvcmos resetb i dd 1 1 i dd tested with clock and data inputs held at v dd or gnd, and i o = 0 ma. v dd 0 v i ddh i ddl v dd /2 10% v dd /2 90% t inact t act input t w input v ih v il v ref v ref
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 10 of 16 propagation delay times output slew rates over r ecommended operating free - air temperature range (unless otherwise noted) v cc = 2.5 v + 0.2v * v cc = 2.6 v + 0.1 v * parameter from to min max min max unit dv/dt_r 20% 80% 1 4 1 4 v/ns dv/dt_f 80% 20% 1 4 1 4 v/ns dv/dt_ ? ?? 20% or 80% 80% or 20% 1 1 v/ns *for this test condition, v ddq is always equal to v dd **difference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate) input v ih v il v ref v ref v icr timing input t s t h v i(pp) v icr v icr timing input output v tt v tt v oh v ol t plh t phl v i(pp) lvcmos resetb input output v ih v il v oh v ol t phl v dd /2 v tt
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 11 of 16
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 12 of 16 package dimensions (64 - pin tssop) 1 2 n index area e1 e e b a1 a d a2 c l aaa c 6.10 mm (240 mil) body, 0.50 mm (0.020 mil) pitch tssop symbol millimeters inches min max min max a C C ? 8 ? 0 ? 8 ? aaa C C seating plane ?
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 13 of 16 0.25 c b d1/2 d1 d/2 d e1/2 e1 e/2 e 0.18 dia. 0.20 c b 0.20 c a 0.25 c a a a1 a3 ? seating plane 4x p 4x p e l (nd - 1) x e (ne - 1) x e e2 e2/2 d2 d2/2 0.25 c a b pin id 0.35 t e rminal tip for odd terminal/side for even terminal/side cross section a1 b a2 top view bottom view side view package dimensions (56 - pin mlf2) symbol common dimensions min typ max a 0.85 1.00 a1 0.00 0.01 0.05 a2 0.65 0.80 a3 0.20 bsc d 8.00 bsc d1 7.75 bsc e 8.00 bsc e1 7.75 bsc q 12 p 0.24 0.42 0.60 r 0.13 0.17 0.23 pitch variation d e 0.50 bs c n 56 nd 14 ne 14 l 0.30 0.40 0.50 b 0.18 0.23 0.30 q 0.00 0.20 0.45 d2 4.35 4.50 4.65 e2 5.05 5.20 5.35
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 14 of 16 ordering information ordering number marking package qty per reel temperature asm4sstvf16859 - 64tt as4sstvf16859t 64 - pin tssop, tube 0 ? c to 70 ? c asm4sstvf16859 - 64tr as4sstvf16859t 64 - pin tssop, tape & reel 2500 0 ? c to 70 ? c asm4sstvf16859 - 56 q t as4sstvf16859 q 56 - pin mlf2 - vqfn , tube 0 ? c to 70 ? c asm4sstvf16859 - 56 q r as4sstvf16859 q 56 - pin mlf2 - vqfn , tape & reel 2500 0 ? c to 70 ? c
august 200 4 asm4sstvf16859 rev 2.0 ddr 13 - bit to 26 - bit registered buffer 15 of 16 ? copyright 200 4 alliance semiconductor corporation. all rights reserved. our three - point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the tr ademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to cha nge or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive informati on for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights , except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance d oes not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life - supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life - supporting systems implies that the manufacturer assumes all risk of such use and agrees to i ndemnify alliance against all claims arising from such use. alliance semiconductor corporation 2595, augustine drive, santa clara, ca 95054 tel# 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved advance information part number: asm4sstvf16859 document version: v 2 .0

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